Process Damage
Process damage can occur during fabrication processing of integrated circuits, this damage may occur even before protective circuits are fully formed, and may result from charge buildup and induced voltages during ion etching, ion implantation, or other process steps involving plasma and charged-particle beams. This process damage may result from induced voltages on on-chip interconnect or other on-chip metal shapes from radio-frequency fields used to ionize gasses during plasma etching, and for other reasons. This charge must dissipate before it reaches levels that may be fatal to circuit elements.
Process damage may result because large metal shapes on integrated circuits (ICs) can serve as antennae, picking up significant induced voltages during processing, particularly during processing involving radio-frequency fields such as sputtering and plasma etching. These induced voltages have potential for causing circuit damage. For example, photosensor array integrated circuits may have a ring of photon-blocking metal that surrounds the photosensor array itself, covering circuitry that is necessary for overall IC operation but operation of which could be adversely affected by light. Large photon-blocking rings can act as antennas, picking up high induced voltages during processing involving such high radio-frequency fields. Damage caused by high induced voltages may irreparably damage structures, such as by rupturing gate oxides and spiking through contacts, on the integrated circuit during such processing steps including plasma-etching of the large photon-blocking ring, or of sputter deposition of additional layers on the integrated circuit.
Among ways such process damage can be minimized during processing of integrated circuits is ensuring all large shapes on metal layers are coupled to diffused areas on the integrated circuit.
Noise, Stray Charges, and Guardrings
Charges in photosensor array circuits can also arise from photons impacting exposed semiconductor areas of a photosensor array circuit. This includes photosensors of the array as well as surrounding circuitry. If allowed to accumulate, these charges can interfere with circuit operation. Similarly, noise can be coupled into sensitive analog circuitry from switching logic circuits through bondwire resistance and current surges, it can be desirable to isolate portions of an integrated circuit with “guardrings”—structures that separate portions of the circuit into digital and analog regions and which serve to isolate sensitive circuitry by absorbing stray charges, although they need not always form a complete ring around the sensitive circuitry.
Bondpads
It is well known in the integrated circuit art that circuitry coupled to bondpads of integrated circuits (ICs) is susceptible to damage when those bondpads become coupled to external conductors that bear an electrostatic charge; such charged conductors may be parts of component testing, handling or assembly machines, workers that must handle the circuits, curious consumers who handle the parts, or even component storage bags or tubes. Typically, integrated circuit designers incorporate electrostatic-discharge (ESD) protective circuitry intended to dissipate such electrostatic charges without damaging their integrated circuit, and part of reliability testing of ICs involves testing their designs for effectiveness. A common ESD test standardized in JS-001-2012 and MIL-STD-883H models a charged human finger by a 100 pF capacitor and a 1500 ohm discharging resistance. During testing, the fully charged capacitor is discharged through the resistor and through bondwires into a bondpad of the integrated circuit; typical testing involves charging the capacitor to 1500 volts or more. Other ESD test models exist, including a machine model and charged device model; testing to the machine model typically involves coupling a charged capacitor to the circuit with no intervening resistor.
ESD may damage integrated circuits in several ways, many of which are irreversible. For example, gate oxide damage typically results because the very thin oxides used in typical integrated circuits can break down-forming a short circuit-if voltage across the oxide exceeds a breakdown-voltage limit that may, for some circuits, be less than ten volts. ESD discharge can also result in momentary high currents at metal-to-semiconductor contacts in on-chip protective circuitry. High contact current can evaporate metal, leaving an open circuit, or cause enough heating at contacts that semiconductor dissolves into metal, leaving spikes of metal that may extend through shallow integrated circuit junctions leaving a short circuit across the junction.
ESD protective devices are often integrated onto ICs to ensure static charges are dissipated without harm, similarly diffused shapes electrically coupled to large metal shapes are often provided to protect circuits from process-related damage from induced voltages and currents that may be picked up on those metal shapes.
Typically, output pad ESD protection incorporates large transistors located near bonding pads. Large transistors are typically provided to drive high output currents associated with outputting signals onto the bonding pads, but where output transistors are smaller than required to absorb electrostatic discharges, parallel dummy transistors are help conduct electrostatic discharges. Discharges typically pass through metal-to-semiconductor contacts into drain regions of these large transistors, then through paths including source-drain punchthrough to ground or power regions, and thence to ground or power metallization. Another path typically followed by discharge current includes a path through a parasitic junction diode beneath the drain of the large transistor into well or substrate regions, and thence through well or substrate contacts into ground or power metallization, or through well-substrate junctions into substrate, and thence through substrate contacts into ground metallization.
Conventional “bulk” complementary metal oxide semiconductor (CMOS) ICs, as well as front-side-illuminated CMOS photosensor array ICs, often have a fairly thick, conductive, substrate that can form a relatively low-impedance path from the parasitic diode to well or substrate contacts.
Backside Illumination
Backside-illuminated CMOS photosensor array ICs, however, must have the substrate thinned so that light can penetrate that part of the substrate lying beneath photosensors of the array, and thereby reach the photosensors. Thinning may be accomplished by techniques including chemical-mechanical milling and etching. Since thinned wafers are too fragile for processing, a front side of the wafer is reinforced with additional silicon.
Thinned silicon substrate does not, however, have the same conductivity of a full-thickness, un-thinned, wafer. In some prior thinned-wafer, backside-illuminated, photosensor ICs 100, as illustrated in FIG. 1, a backside metallization 102, with backside grounding contacts 104 penetrating a backside dielectric layer 103 to the thinned substrate 106, is used to provide a discharge path for electrostatic discharges, however in some cases current crowding in specific drain contacts during a discharge, whether from ESD or induced voltages during processing, results in circuit damage. Backside metallization 102 also typically serves as a photon blocking layer, with openings over photosensors of the array and photon-blocking metal over non-photosensor devices, such as selection transistors, and over peripheral circuitry, such as row and column counters, decoders and sense amplifiers, associated with the array. Similarly, the backside metallization 102 may block photons from reaching any other circuitry, such as signal processing circuitry, that may be collocated on the photosensor IC. These photosensor ICs may have the original substrate 106 removed in bondpad areas 108 to permit pad metal 110 to have easy access to first layer interconnect metal 112, first layer interconnect metal 112 in turn couples to diffused drain areas 116 of large transistors formed by silicon gate 114 and drain 116, and source 118 diffusions, which may be N+ diffusions lying in an optional well, such as a P well 120. Typically, substrate 106 is weakly P-type, and some output devices typically also have source and drain diffusions that are P+ diffusions lying in N− wells (not shown), as known in the CMOS art. Interconnect metal 112 is in one or more layers of one or more insulating dielectrics 124, which may also contain additional interconnect metal layers, and an additional silicon structural layer 122 is provided to give the device some mechanical strength. An array of photosensors 126, at least part of each photosensor exposed through an opening in backside metal 102, are provided on the circuit to permit imaging.